Technical Field
The present invention relates to stacked-channel field effect transistors and, more particularly, to the use of a sacrificial layer to improve retention of top channel layers.
Description of the Related Art
Stacked nanowire and nanosheet devices are proposed for modern and next-generation semiconductor devices. The devices are formed around thin channel materials, configured as either wires or sheets of semiconductor material. Parasitic capacitance in nanosheet devices is a significant performance detractor, which can be mitigated through the formation of an inner spacer between a gate stack and the source and drain regions.
However, the dummy gate processes used to form stacked nanowire and nanosheet devices can cause significant damage to the small-scale channel structures. In particular, etching processes used to remove dummy gate structures and form inner spacers are not perfectly selective and damages the top layer of a nanowire or nanosheet channel. In many cases, the top layer of a channel is destroyed entirely by the process.